"Error (10500): VHDL syntax error at mag_comp.vhd(15) near text "AGTB"; expecting ";"

Message. I followed the directions to line 15 and I don't need a ";" at the end. When I humor the program and add one anyways it gives me more errors. Quartus has never really been straightforward with me about errors in coding, so I thought I'd post it here to get a second opinion:

Code:

```
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;
```

As a side note, AEQB is 'equal to', AGTB is 'greater than', and ALTB is 'less than'.