Re: VHDL magnitude comparitor
Hello Prototape.
Not sure if this is it, but maybe you should add ';' at the end of the line that has:
Hello Prototape.
Not sure if this is it, but maybe you should add ';' at the end of the line that has:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF mag_comp IS
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
END IF;
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
END IF;
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
END IF;
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
END IF;
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
END IF;
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
END IF;
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
END IF;
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 : IN STD_LOGIC;
AEQB, AGTB, ALTB : OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0';
AGTB <= '1';
ALTB <= '0';
ELSIF (a2 < b2) THEN
AEQB <= '0';
AGTB <= '0';
ALTB <= '1';
ELSE
AEQB <= '1';
AGTB <= '0';
ALTB <= '0';
END IF;
IF (a1 > b1) THEN
AEQB <= '0';
AGTB <= '1';
ALTB <= '0';
ELSIF (a1 < b1) THEN
AEQB <= '0';
AGTB <= '0';
ALTB <= '1';
ELSE
AEQB <= '1';
AGTB <= '0';
ALTB <= '0';
END IF;
IF (a0 > b0) THEN
AEQB = '0';
AGTB = '1';
ALTB = '0';
ELSIF (a0 < b0) THEN
AEQB = '0';
AGTB = '0';
ALTB = '1';
END IF;
END PROCESS;
END behavior;
From quickly looking at my only HDL book with VHDL (I've primarily done Verilog), it looks like you need semicolons at the end of all of the statements in bold. I would not be surprised if the number of errors goes up before you finish fixing them. Your code should basically end up looking like what AlbertMC2 posted.I followed the directions to line 15 and I don't need a ";" at the end. When I humor the program and add one anyways it gives me more errors. Quartus has never really been straightforward with me about errors in coding, so I thought I'd post it here to get a second opinion:
Code:LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mag_comp IS PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC; AEQB, AGTB, ALTB :OUT STD_LOGIC); END mag_comp; ARCHITECTURE behavior OF mag_comp IS BEGIN PROCESS (a2, b2, a1, b1, a0, b0) BEGIN IF (a2 > b2) THEN [B] AEQB <= '0' AGTB <= '1' ALTB <= '0'[/B] ELSIF (a2 < b2) THEN [B] AEQB <= '0' AGTB <= '0' ALTB <= '1'[/B] ELSE (a2 = b2) THEN [B] AEQB <= '1' AGTB <= '0' ALTB <= '0'[/B] IF (a1 > b1) THEN [B] AEQB <= '0' AGTB <= '1' ALTB <= '0'[/B] ELSIF (a1 < b1) THEN [B] AEQB <= '0' AGTB <= '0' ALTB <= '1'[/B] ELSE (a1 = b1) THEN [B] AEQB <= '1' AGTB <= '0' ALTB <= '0'[/B] IF (a0 > b0) THEN [B] AEQB = '0' AGTB = '1' ALTB = '0'[/B] ELSIF (a0 < b0) THEN [B] AEQB = '0' AGTB = '0' ALTB = '1'[/B] END IF; END PROCESS; END behavior;