Re: VHDL magnitude comparitor
Hello Prototape.
Not sure if this is it, but maybe you should add ';' at the end of the line that has:
Hello Prototape.
Not sure if this is it, but maybe you should add ';' at the end of the line that has:
[SOLVED] VHDL magnitude comparitor
I wrote a code for a magnitude comparitor, and it looks fine to me (though I'm a bit sketchy on VHDL). I'm trying to compile it with Quartus II but it's giving me an:
"Error (10500): VHDL syntax error at mag_comp.vhd(15) near text "AGTB"; expecting ";"
Message. I followed the directions to line 15 and I don't need a ";" at the end. When I humor the program and add one anyways it gives me more errors. Quartus has never really been straightforward with me about errors in coding, so I thought I'd post it here to get a second opinion:
If anyone sees any syntax errors in this I would appreciate it if you'd let me know. I'm somewhat new to VHDL.
As a side note, AEQB is 'equal to', AGTB is 'greater than', and ALTB is 'less than'.
"Error (10500): VHDL syntax error at mag_comp.vhd(15) near text "AGTB"; expecting ";"
Message. I followed the directions to line 15 and I don't need a ";" at the end. When I humor the program and add one anyways it gives me more errors. Quartus has never really been straightforward with me about errors in coding, so I thought I'd post it here to get a second opinion:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;As a side note, AEQB is 'equal to', AGTB is 'greater than', and ALTB is 'less than'.
- Status
- Not open for further replies.
1 - 7 of 7 Posts
Re: VHDL magnitude comparitor
Didn't work :/ You don't typically do that at the end of a statement like that in VHDL. Not sure why, but that's just how it is I guess. I'm not too clear on what dictates putting a ';' at the end of stuff. In my text it says you should always do it, but that's not the case. My book is useless :L
I appreciate the suggestion, though :smile:
Didn't work :/ You don't typically do that at the end of a statement like that in VHDL. Not sure why, but that's just how it is I guess. I'm not too clear on what dictates putting a ';' at the end of stuff. In my text it says you should always do it, but that's not the case. My book is useless :L
I appreciate the suggestion, though :smile:
Re: VHDL magnitude comparitor
Hello!
I have never used VHDL or Quartus before, so this is almost certainly wrong as well, but maybe the compiler is going through line by line, and is erroring at the first incorrect line only. What I mean by this, is what if all of the red highlighted lines are erroring:
The second (+/- the third line) of each if statement.
In a lot of languages, you are allowed 1 line IF statements, otherwise you need to open and close the parenthesis.
Maybe it is erroring on the second line with a generic "Close expression" error. Does (and it probably doesn't) the below code solve the issue:
Richard
Hello!
I have never used VHDL or Quartus before, so this is almost certainly wrong as well, but maybe the compiler is going through line by line, and is erroring at the first incorrect line only. What I mean by this, is what if all of the red highlighted lines are erroring:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;In a lot of languages, you are allowed 1 line IF statements, otherwise you need to open and close the parenthesis.
Maybe it is erroring on the second line with a generic "Close expression" error. Does (and it probably doesn't) the below code solve the issue:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC;
AEQB, AGTB, ALTB :OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
END IF;
ELSIF (a2 < b2) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
END IF;
ELSE (a2 = b2) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
END IF;
IF (a1 > b1) THEN
AEQB <= '0'
AGTB <= '1'
ALTB <= '0'
END IF;
ELSIF (a1 < b1) THEN
AEQB <= '0'
AGTB <= '0'
ALTB <= '1'
END IF;
ELSE (a1 = b1) THEN
AEQB <= '1'
AGTB <= '0'
ALTB <= '0'
END IF;
IF (a0 > b0) THEN
AEQB = '0'
AGTB = '1'
ALTB = '0'
END IF;
ELSIF (a0 < b0) THEN
AEQB = '0'
AGTB = '0'
ALTB = '1'
END IF;
END PROCESS;
END behavior;Re: VHDL magnitude comparitor
Hi
I would imagine it is:
Your last IF statement does not have a (a0 = b0) option (maybe by design?)
I do not know VHDL but used examples from:
VHDL coding tips and tricks
and
Digital Systems Design Using VHDL (PDF Slides)
Hi
I would imagine it is:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mag_comp IS
PORT ( a2, b2, a1, b1, a0, b0 : IN STD_LOGIC;
AEQB, AGTB, ALTB : OUT STD_LOGIC);
END mag_comp;
ARCHITECTURE behavior OF mag_comp IS
BEGIN
PROCESS (a2, b2, a1, b1, a0, b0)
BEGIN
IF (a2 > b2) THEN
AEQB <= '0';
AGTB <= '1';
ALTB <= '0';
ELSIF (a2 < b2) THEN
AEQB <= '0';
AGTB <= '0';
ALTB <= '1';
ELSE
AEQB <= '1';
AGTB <= '0';
ALTB <= '0';
END IF;
IF (a1 > b1) THEN
AEQB <= '0';
AGTB <= '1';
ALTB <= '0';
ELSIF (a1 < b1) THEN
AEQB <= '0';
AGTB <= '0';
ALTB <= '1';
ELSE
AEQB <= '1';
AGTB <= '0';
ALTB <= '0';
END IF;
IF (a0 > b0) THEN
AEQB = '0';
AGTB = '1';
ALTB = '0';
ELSIF (a0 < b0) THEN
AEQB = '0';
AGTB = '0';
ALTB = '1';
END IF;
END PROCESS;
END behavior;I do not know VHDL but used examples from:
VHDL coding tips and tricks
and
Digital Systems Design Using VHDL (PDF Slides)
Re: VHDL magnitude comparitor
This could be wrong since I haven't done much VHDL, but I'd think of the IF ... END IF; and BEGIN ... END SOMETHING; as a single statement that happen to contain more statements between the start and end. I assume ARCHITECTURE is like an if statement in C that expects a statement to follow and the BEGIN ... END SOMETHING; basically is the same as a block in C (curly braces { ... }). I am ignoring whether or not VHDL requires that the statement be a BEGIN block or if it allows any other statement to follow like if statements in C. I'd have to read the IEEE standard to know.
So basically all statements should have semicolons at the end, but some statements can contain more statements. Although this is just guessing based on using a variety of other languages, looking at a little VHDL in one of my textbooks, and thinking about how I'd specify a grammar for a parser generator. I'm probably ignoring something about VHDL, but I'd expect that to be close.
What VHDL book are you using?
From quickly looking at my only HDL book with VHDL (I've primarily done Verilog), it looks like you need semicolons at the end of all of the statements in bold. I would not be surprised if the number of errors goes up before you finish fixing them. Your code should basically end up looking like what AlbertMC2 posted.I followed the directions to line 15 and I don't need a ";" at the end. When I humor the program and add one anyways it gives me more errors. Quartus has never really been straightforward with me about errors in coding, so I thought I'd post it here to get a second opinion:
Code:LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mag_comp IS PORT ( a2, b2, a1, b1, a0, b0 :IN STD_LOGIC; AEQB, AGTB, ALTB :OUT STD_LOGIC); END mag_comp; ARCHITECTURE behavior OF mag_comp IS BEGIN PROCESS (a2, b2, a1, b1, a0, b0) BEGIN IF (a2 > b2) THEN [B] AEQB <= '0' AGTB <= '1' ALTB <= '0'[/B] ELSIF (a2 < b2) THEN [B] AEQB <= '0' AGTB <= '0' ALTB <= '1'[/B] ELSE (a2 = b2) THEN [B] AEQB <= '1' AGTB <= '0' ALTB <= '0'[/B] IF (a1 > b1) THEN [B] AEQB <= '0' AGTB <= '1' ALTB <= '0'[/B] ELSIF (a1 < b1) THEN [B] AEQB <= '0' AGTB <= '0' ALTB <= '1'[/B] ELSE (a1 = b1) THEN [B] AEQB <= '1' AGTB <= '0' ALTB <= '0'[/B] IF (a0 > b0) THEN [B] AEQB = '0' AGTB = '1' ALTB = '0'[/B] ELSIF (a0 < b0) THEN [B] AEQB = '0' AGTB = '0' ALTB = '1'[/B] END IF; END PROCESS; END behavior;
This could be wrong since I haven't done much VHDL, but I'd think of the IF ... END IF; and BEGIN ... END SOMETHING; as a single statement that happen to contain more statements between the start and end. I assume ARCHITECTURE is like an if statement in C that expects a statement to follow and the BEGIN ... END SOMETHING; basically is the same as a block in C (curly braces { ... }). I am ignoring whether or not VHDL requires that the statement be a BEGIN block or if it allows any other statement to follow like if statements in C. I'd have to read the IEEE standard to know.
So basically all statements should have semicolons at the end, but some statements can contain more statements. Although this is just guessing based on using a variety of other languages, looking at a little VHDL in one of my textbooks, and thinking about how I'd specify a grammar for a parser generator. I'm probably ignoring something about VHDL, but I'd expect that to be close.
What VHDL book are you using?
Re: VHDL magnitude comparitor
The book I'm using is Digital Design with CPLD Applications and VHDL.
I tried the one with the added semicolons but it gave me a lot of errors. I ended up figuring out what I did wrong, I wasn't supposed to group the outputs in the Entity section.
Thanks for the help, though
The book I'm using is Digital Design with CPLD Applications and VHDL.
I tried the one with the added semicolons but it gave me a lot of errors. I ended up figuring out what I did wrong, I wasn't supposed to group the outputs in the Entity section.
Thanks for the help, though
1 - 7 of 7 Posts
- Status
- Not open for further replies.
Tech Support Forum
A forum community dedicated to tech experts and enthusiasts. Come join the discussion about articles, computer security, Mac, Microsoft, Linux, hardware, networking, gaming, reviews, accessories, and more!
Full Forum Listing
Recommended Communities
