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Pipelined processor decode stage

1K views 2 replies 2 participants last post by  Ninjaboi 
#1 ·
Hello,

I am new to vhdl, and I want to get some help with the instruction decode stage of a simple processor architecture that has 26 instructions (instructions are 16 bits long). I have already described instruction fetch stage in VHDL, but I am not sure where to proceed in this stage. If anyone has any experience with this I appreciate any help, thanks. What are the general concepts to work on? How do I manage the different types of instructions? etc.
 
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